module IF_reg(
  input clk,
  input rst,
//pipeline signals
  input flush,
  input enable,
  input ready,

//from Fetch unit
  input valid_i,
  input [63:0] inst_pc_i,
  input [31:0] inst_i,

//to Decode uint
  output [63:0] inst_pc_o,
  output [31:0] inst_o/*verilator public_flat*/ ,
  output valid_o

);

  Reg #(.WIDTH(64), .RESET_VAL(64'b0)) reg_inst_pc (.clk(clk), .rst(rst), .din(inst_pc_i), .dout(inst_pc_o), .wen(enable));

  wire [31:0] inst_last;
  wire inst_valid_last;
  Reg #(.WIDTH(32), .RESET_VAL(32'b0)) reg_inst_last (.clk(clk), .rst(rst), .din(inst_i), .dout(inst_last), .wen(valid_i));
  Reg #(.WIDTH(1), .RESET_VAL(1'b0)) reg_inst_valid_last (.clk(clk), .rst(rst|ready), .din(valid_i), .dout(inst_valid_last), .wen(valid_i));

  assign inst_o = {32{valid_i}}&inst_i | {32{~valid_i}}&inst_last;
  assign valid_o = valid_i&ready;
  
endmodule
